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| INDEX MX8810 Motion-JPEG Real Time Video CODEC LSI Product Specification P/N:PM0363 REV. 1.0, AUG. 25, 1998 1 INDEX MX8810 1. OUTLINE Real Time Video Codec LSI is a LSI chip which can compress/decompress high performace still image and motion picture data. The method of Encode/Decode is based on JPEG, an international standard encode/decode method for color still image. Features: * Compression/Decompression of high performace still image & motion picture data. (High Speed) * for color image, 14.3MHz/Pixel high speed * for grey level image, 28.6MHz/Pixel high speed * real time process for color image and grey level image (full frame [30 frames/sec], full screen [768x480 : NTSC] in case of DMA mode) (High Quality Image) * block distortion detection function * real time process even in high quality mode. (full frame [30 frames/sec], full screen [768x480 : NTSC] in case of DMA mode ) * Total cost down for the system (Minimize external circuit & packaging area) * can directly connect with NTSC signal encoder/decoder without frame memory. * comprssion/decompression functions in one chip * color space conversion function * control function of buffer memory for raster block conversion * For the system without cpu, it provides independent board and separated cpu I/F and compression data I/ F. * Others * field decision function * power down function * standard Y quantization table/ standard C quantization table (user definable) * quantization table scale function * standard Y huffman table/ standard C huffman table * 32bits/16bits DMA mode or synchronous mode can be used in data compression I/O. * chroma-key detection * maximum system clock = 28.6MHz * 160 pins QFP * 5V single power supply Application: * * * * * * * CATV High-Speed Video Camera Animation process board for PC TV Security Camera Digital Still Video Camera Image Editor P/N:PM0363 REV. 1.0, AUG. 25, 1998 2 INDEX MX8810 2.PIN CONFIGURATION 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 MOA6 MOA5 MOA4 M0A3 M0A2 M0A1 M0A0 VCC M0WEB M0OEB M0D0 M0D1 M0D2 M0D3 M0D4 M0D5 M0D6 M0D7 M2D GND GND M1A13 M1A12 M1A11 M1A10 M1A9 M1A8 M1A7 M1A6 M1A5 M1A4 M1A3 M1A2 M1A1 M1A0 M1WEB M1OEB M1D0 M1D1 M1D2 MOA7 MOA8 MOA9 MOA10 MOA11 MOA12 MOA13 GND CRKEY BLOCK PREQ P2D0 P2D1 P2D2 GND P2D3 GND GND VCC P2D4 P2D5 P2D6 P2D7 P1D0 P1D1 P1D2 P1D3 P1D4 P1D5 P1D6 P1D7 P0D0 P0D1 P0D2 P0D3 P0D4 P0D5 P0D6 P0D7 PVALID 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 MX8810 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 M1D3 M1D4 M1D5 M1D6 M1D7 M3D CVALID CREQ CDATA31 CDATA30 CDATA29 CDATA28 CDATA27 CDATA26 VCC CDATA25 CDATA24 GND VCC CDATA23 CDATA22 CDATA21 CDATA20 CDATA19 CDATA18 CDATA17 CDATA16 CDATA15 CDATA14 CDATA13 CDATA12 CDATA11 CDATA10 CDATA9 CDATA8 GND CDATA7 CDATA6 CDATA5 CDATA4 P/N:PM0363 VSYNC HSYNC DIR INTB PWDN RDB WRB CSB DATA0 DATA1 DATA2 DATA3 DATA4 VCC GND DATA5 DATA6 DATA7 ADD0 ADD1 ADD2 ADD3 ADD4 ADD5 ADD6 ADD7 RESETB CLK DMARDB GND VCC DMAWRB WAITB DTENDB DMARQB EOF CDATA0 CDATA1 CDATA2 CDATA3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 REV. 1.0, AUG. 25, 1998 3 P/N:PM0363 3.BLOCK DIAGRAM PREQ PVALID BLOCK CRKEY P0D(7:0) P1D(7:0) P2D(7:0) Pixel I/F DIR VSYNC Color Space Conversion System Control I/F HSYNC PWDN RESETB CLK Sample Conversion INTB RDB WRB CSB DATA(7:0) ADD(7:0) Q-table CPU I/F M0A(13:0) M0WEB M0OEB M0D(7:0) M2D Raster Block Convert I/F Q-table 4 Huffman table WAITB DMAWRB DMARDB M1A(13:0) M1WEB M1OEB M1D(7:0) M3D DCT Conversion Quantization/Dequantization Huffman Encode/Decode Compression data I/F CDATA CREQ EOF DMAREOB DTENDB CVALID MX8810 REV. 1.0, AUG. 25, 1998 INDEX INDEX MX8810 4.PIN DESCRIPTION 4-1 Pin Definition Table PIN NO 1 2 3 4 5 6 7 8 9~13,16~18 19~26 27 28 29 32 33 34 35 36 37~44,46~61,64~65,67~72 73 74 75 76~83 84 85 86~99 102 103~110 111 112 114~127 129 130 SYMBOL VSYNC HSYNC DIR INTB PWDN RDB WRB CSB DATA0~DATA7 ADD0~ADD7 RESETB CLK DMARDB DMAWRB WAITB DTENDB DMAREQB EOF CDATA0~CDATA31 CREQ CVALID M3D M1D0~M1D7 M1OEB M1WEB M1A0~M1A13 M2D M0D0~M0D7 M0OEB M0WEB M0A0~M0A13 CRKEY BLOCK I/O IN IN OUT OD IN IN IN IN IO IN IN IN IN IN OUT OD OUT OUT I/O OUT OUT IO IO OUT OUT OUT IO IO OUT OUT OUT OUT OUT 4 4 4 4 4 4 4 2 2 2 2 2 2 2 2 2 2 2 2 4 4 4 OUT TYPE P/N:PM0363 REV. 1.0, AUG. 25, 1998 5 INDEX MX8810 PIN NO 131 132~134,136,140~143 144~151 152~159 160 14,31,62,66,113,139 15,30,45,63,100,101,128,135, 137,138 SYMBOL PREQ P2D0~P2D7 P1D0~P1D7 P0D0~P0D7 PVALID VCC GND I/O OUT IO IO IO OUT POWER POWER OUT TYPE 2 2 2 2 2 I/O: IN:TTL level input OUT:output IO:TTL level I/O OD:open dr OUTPUT TYPE: 2:Iol = 2mA/Ioh = -1mA 4:Iol = 4mA/Ioh = -2mA P/N:PM0363 REV. 1.0, AUG. 25, 1998 6 INDEX MX8810 4-2. Pin Function Description * PREQ [OUT] Pixel data access busy signal) If it is "H", pixel data access busy when CLK is active. * PVALID [OUT] (Pixel data valid signal) If it is "H", pixel data output is valid when CLK is active. * BLOCK [OUT] (Block distortion detection signal) If it is "H", block distortion is predictable for pixel data when CLK is active. * CRKEY [OUT] (Chroma-key signal) If it is "H", chroma-key is detected for pixel data when CLK is active. P/N:PM0363 REV. 1.0, AUG. 25, 1998 7 INDEX MX8810 P/N:PM0363 REV. 1.0, AUG. 25, 1998 8 INDEX MX8810 * RESETB [IN] (Hardware reset signal) If it is "L", hardware reset will be executed. Internal circuit will be initialized and internal register will be set by default value. In the period of hardware reset, all I/O pins will be changed to input mode. * PWDN [IN] (Power down signal) If it is "H", change to the power down mode. * HSYNC [IN] (Horizontal synchronous signal) Horizontal synchronous signal input. (positive) * VSYNC [IN] (Vertical synchronous signal) Vertical synchronous signal input. (positive) * DIR [OUT] (Interface direction signal) If it is "H", pixel I/F is input mode and compression data I/F is output mode. If it is "L", pixel I/F is output mode and compression data I/F is input mode. (Power supply) (Ground) P/N:PM0363 REV. 1.0, AUG. 25, 1998 9 INDEX MX8810 5. FUNCTION DISCRIPTION 5-1.FUNCTIONS 5-1-1. Pixel I/F Data input/output, based on HSYNC/VSYNC valid data area. Corresponding formats are o RGB format o YCrCb format o YC format o Y0Y1 format 5-1-2. Color Space Conversion RGB space <---> YCrCb space conversion 5-1-3. Sample Conversion In compression, 1/2 thin out Cr and Cb in horizontal direction then multiplex it. In decompression, demultiplex Cr and Cb then execute previous value interpolation in horizontal direction. 5-1-4. Raster Block Convert I/F Interface to external memory for the conversion of raster order <---> 8x8 block order. 5-1-5. Quantization Table Standard Y table and Standard C table is equipped for the quantization table. User can also select his own user-define Y table/ user-define C table. 5-1-6. Quantization Table Scale In standard quantization table and user define quantization table, each value is uniformly scalable. 5-1-7. Huffman Table Standard Y table/ Standard C table is equipped. 5-1-8. Compression Data I/F Compression data I/O in synchronous mode or DMA mode. In synchronous mode, it operates at all compression rate in case of no processing enor. But, in decompression, the frequency of clock is limited by the AC characterization. In case of DMA mode, 16 bits or 32 bits bus width for selection. And 28.6MHz is the upper limit of operation, but in case of processing error, the compression rate will be limited. . 5-1-9. Power Down Stop providing clock to internal circuit in order to save power consumption. 5-1-10. Field Decision Interlace/nointerlace decision from horizontal synchronous signal and vertical synchronous signal. In case of interlace, first field is the beginning of compression / decompression. 5-1-11. Block Distortion Detection It can detect the block which is possibly a distorted block in decompression. From detected result, block distortion could be amended by external filter control. 5-1-12. Chroma-key Detection In case of decompression, chroma-key could be detected. P/N:PM0363 REV. 1.0, AUG. 25, 1998 10 INDEX MX8810 5-2. Block Functions 5-2-1. Pixel I/F Pixel I/F provides Input/Output for the data based on HSYNC/VSYNC valid data area on defined pixel format. In case of compression, set PERQ "H" and access pixel data when CLK is active. In case of decompression, if set PVAILD "H" vaild pixel data is exported. The corresponding formats are * RGB format * YCrCb format * YC format * Y0Y1 format 5-2-2. Color Space Conversion In case that RGB format is selected to be pixel format, RGB space <--->YCrCb space conversion will be executed. In case of other pixel formats, there is no conversion. R0 R1 R2 R3 ... <---> Y0 Y1 Y2 Y3... G0 G1 G2 G3 ... <---> Cr0 Cr1 Cr2 Cr3... B0 B1 B2 B3 ... <---> Cb0 Cb1 Cb2 Cb3... Moreover, In case of decompression, chroma-key detection is executed. 5-2-3. Sample Conversion When RGB format and YCrCb format are selected to be a pixel format, in compression, 1/2 thin out Cr and Cb in horizontal direction then multiplex it. In decompression, demultiplex Cr and Cb then execute previous value interpolation. There is no conversion in other pixel formats. Compression: Y0 Y1 Y2 Y3.... --- > Y0 Y1 Y2 Y3 ... . Cr0 Cr1 Cr2 Cr3.... ---> -- Cr0 Cb0 Cr2 Cb2... Cb0 Cb1 Cb2 Cb3....---- ----> -- --> Deompression: Y0 Y1 Y2 Y3.... <--- Y0 Y1 Y2 Y3... Cr0 Cr0 Cr2 Cr2.... <--- Cr0 Cb0 Cr2 Cb2.... Cb0 Cb0 Cb2 Cb2.... <--5-2-4. Raster Block Convert I/F Interface to external memory for raster order <---> 8x8 block order conversion. 5-2-5. DCT Conversion 8x8 image block <---> DCT factor 2-dimension DCT conversion. 5-2-6. Quantization / Dequantization ZIGZAG conversion and quantization / dequantization are executed here. We can select ROM's standard Y table / standard C table or RAM's user Y table / user C table to be quantization table. Each value of selected table is scalable uniformly by the scale factor setting. Moreover, in case of decompression, the block which is possibly a distorted block will be detected. From the detected result, block distortion could be amended by external filter control. 5-2-7. Huffman Encode/Decode In case of compression, huffman encode the quantized DCT factor to compression data. In case of decompression, huffman decode the compressed data. Huffman table is equipped as standard Y table / standard C table. P/N:PM0363 REV. 1.0, AUG. 25, 1998 11 INDEX MX8810 5-2-8. Compression Data I/F Compression data' I/O in synchronous mode or DMA mode. * Synchronous mode 32 bits bus width. In case of compression, if CVALID = "H", valid compression data is exported. In case of decompression, if CREQ = "H" and CLK is active, access compression data. * DMA mode 16 bits or 32 bits bus width. 2k bytes compression data FIFO. Compression: If compression data FIFO is not empty, set DMAREQB "L". If compression data FIFO is empty, set DMAREQB "H". When compression data FIFO is not empty, if DMARDB = "L", valid compression data is exported. When compression data FIFO is empty, if DMARDB = "L", WAITB will be "L". When changing to nonempty, WAITB will change to "H" and valid compression data is exported. For each image's last compression data, if DMARDB = "L", DTENDB change to "L". (If DMARDB change to "H" DTENDB will be "Z") Decompression: If compression data FIFO is not full, set DMAREQB "L". If compression data FIFO is full, set DMAREQB "H". When compression data FIFO is not full, if DMAWRB = "L", access compression data when DMAWRB is active. When compression data FIFO is full, if DMAWRB = "L", WAITB will be "L". When changing to "H" not full, WAITB change to access compression data when DMARDB is active. 5-2-9. CPU I/F Parameters' setting. Set values to the internal registers using 8 bits address bus and 8 bits data bus. 5-2-10. System Control I/F Control hardware reset, power down and field decision functions. Field decision function is executed in 7th line's HSYNC from VSYNC. Output of I/O direction of Pixel I/F and compression data I/F. P/N:PM0363 REV. 1.0, AUG. 25, 1998 12 INDEX MX8810 5-3. External Interface 5-3-1. Pixel I/F Pixel I/F provides Input/Output for the data based on HSYNC/VSYNC valid data area on defined pixel format. I/O rate is 1/2 of system clock's frequency. Compression: export "H" to PREQ, access pixel data while CLK is active. Decompression: If PVALID = "H", valid pixel data is exported. Refer when CLK is active. Moreover, detection result output to BLOCK and the result of chroma-key detection output to CRKEY. RGB format R,G,B=raster order data , 8bits positive number CLK P0D P1D P2D R0 G0 B0 R1 R2 G2 B2 R3 R4 R5 G5 B5 ... ... ... G1 B1 G3 B3 G4 B4 YCrCb format Y=raster order data , 8bits positive number Cr,Cb=raster order data , 8bits 2'complement CLK P0D P1D P2D Y0 Cr0 Cb0 Y1 Cr1 Cb1 Y2 Cr2 Cb2 Y3 Cr3 Cb3 Y4 Cr4 Cb4 Y5 Cr5 Cb5 ... ... ... YC format Y=raster order data , 8bits positive number C=raster order data with Cr,Cb half-and-half, 8bits 2'complement CLK P0D P1D P2D Y0 Cr0 Y1 Cb0 Y2 Cr2 Y3 Cb2 Y4 Cr4 Y5 Cb4 ... ... Pullup or Pulldown Y0Y1 format Y0=raster order even number data , 8bits positive number Y1=raster order O&D data , 8bits 2'complement CLK P0D P1D P2D Y0 Y1 Y2 Y4 Y6 Y8 Y10 Y11 ... ... Y3 Y5 Y7 Y9 Pullup or Pulldown P/N:PM0363 REV. 1.0, AUG. 25, 1998 13 INDEX MX8810 5-3-2. Raster Block Convert I/F The I/O of control signal (address, write enable, output enable) and bidirection data to external memory. Use SRAM to be an external memory, the direct connection is possible. (e.g. refer " 6-1, External memory for raster block") 5-3-3. Compression Data I/F The Input/Output of compression data in synchronous mode or DMA mode. * Synchronous mode 32 bits bus width. Compression: If CVALID = "H", compression data is exported. Refer when CLK is active. Moreover, DTENDB and each image's last compression data will be exported at the same time. Decompression: When CREQ = "H" and CLK is active, compression data access busy. * DMA mode 16 bits bus width or 32 bits bus width. In case of 16 bits, CDATA15 ~ CDATA0 are I/O of compression data. (CDATA31 ~ CDATA16 are used as pull up or pull down) Compression: 1) Read access No matter DMAREQB is L or H, Set DMARDB "L" and confirm WAITB = "H", then refer to valid compression data while DMARDB is active. 2) DMA demand Set DMARDB "L" when DMAREQB = "L", then refer valid compression data while DMARDB is active. When DMAREQB = "H", read will not be executed. 3) DMA burst Begin to read when DMAREQB = "L", if WAITB = "L" DMARDB keeps "L" untill WAITB changes to "H". When DTENDB change to "L", reading stop. Deompression: 1) Write access No matter DMAREQB is L or H, Set DMAWRB "L" and confirm WAITB = "H", then write compression data while DMAWRB is active. 2) DMA demand Set DMAWRB "L" when DMAREQB = "L", then write compression data while DMAWRB is active. When DMAREQB = "H", write will not be executed. 3) DMA burst Begin to write when DMAREQB = "L", if WAITB = "L" DMAWRB keeps "L" untill WAITB changes to "H". P/N:PM0363 REV. 1.0, AUG. 25, 1998 14 INDEX MX8810 * I/O format of compression data Each image's I/O compression data are constructed by quantization table scale block, compression data block and image ending block. o Quantization table scale block constructed by 24 bits data (00h,00h,00h) and 8 bits quanttization table scale factor (SF). o Compression data block constructed by compression data which the marker is deleted (byte strip) from JPEG data. o Image ending block constructed by 32 bits data (00h,00h,00h,00h). Synchronous and 32bits DMA mode 16bits DMA mode 00h Time 00h 00h SF Quantization Scale block 00h 00h SF* 00h Quantization Scale block Compression data block Image ending block 00h C D A T A 31 00h 00h 00h C D A T A 0 Time Compression data block ........... 00h 00h C D A T A 15 00h 00h C D A T A 0 Image ending block ..... SF:8bits' quantization table scalefacton P/N:PM0363 REV. 1.0, AUG. 25, 1998 15 INDEX MX8810 5-3-4. CPU I/F Parameters' setting is executed here. Set values to the internal registers using 8 bits address bus and 8 bits data bus. * Address Map REGISTER Command Mode Scale factor Horizontal dot cycle Horizontal valid dot delay Horizontal valid dot width Vertical line cycle Vertical valid line delay Vertical valid line width Status Interrupt mask Y detection Cr detection Cb detection Y detect mask Cr detect mask Cb detect mask Y quantization table Address MAP 00 01 02 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 80 BF C0 FF R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSB STA DET - bit6 DMA - bit5 ESC - bit4 WID (7:0) HCY HDL VCY VCY VDL VWD ERR MER YQ00 YQ63 CQ00 CQ63 bit3 - bit2 PFM HCY bit1 - LSB SRB ENC (11:8) (18:8) (7:0) HDL (7:0) HWD (7:0) VCY (7:0) VDL (7:0) (7:0) (7:0) (7:0) (7:0) (7:0) VWD (10:8) (10:8) (11:8) (10:8) - - - FIN MFI YDT CRD CBT MYD MCR MCB FUL MFU (7:5) (7:5) (7:5) (7:5) (7:5) (7:5) EMP MEM C quantization Note: When address="03" or "18-7F" please don't read and write. P/N:PM0363 REV. 1.0, AUG. 25, 1998 16 INDEX MX8810 * Command register Control start/finish of compression/decompression and software reset process. STArt Soft ReseT_B Function Start S/W reset H Start release L Stop reset S/W reset Previous value / H/W reset L H STA(bit7): refer STA while VSYNC rises to "H" when CLK is active. (refer the following figure) If it is 1, wait for first field then start the process. If it is 0, process current field then finish. VSYNC CLK 1 2 3 1) VSYNC rises to "H" when CLK is active, refer STA. 2) Because VSYNC do not change from "H" when CLK is active, do not refer STA. 3) Because VSYNC is "L" when CLK is active, do not refer STA . SRB(bit0): If set it to 0, software reset process starts. Set it to 1 when software reset process is over. Software reset will cause process compulsory interrupt,releasing process error and clearing internal compression data FIFO. P/N:PM0363 REV. 1.0, AUG. 25, 1998 17 INDEX MX8810 * Mode Register Mode control for Compression / Decompression, Pixel I/F, Compression data I/F and Quantization table(Qtable). Function H L S/W reset H/W reset Default -Table Q-Table ROM RAM Previous Value H DMA DMA/Sync DMA Sync Previous Value H WIDe bus DMA pulse width 32bit 16bit Previous Value L Pix ForMat Pixel I/F Format Data Previous Value 6h EnCode/ Compression/ Compression DCcompression Previous Value H decode Decompression DFT(bit7): If set it to 1, standard Q-table will be selected. If set it to 0, user define Q-table will be selected. When user define Q-table is selected, you must setup values to the table. DMA(bit6): If set it to 1, DMA mode of compression data I/F will be selected. If set it to 0, synchronous mode of compression data I/F will be selected. WID(bit4): It is valid while DMA mode of compression data I/F is selected. If set it to 1, 32 bits DMA will be selected. If set it to 0, 16 bits DMA will be selected. PFM(bit3-0): Use the following value to select pixel I/F format. RGB format = 7h YCrCb format= 6h YC format = 4h Y0Y1 format = 0h P.S.) please do not use the other values. ENC(bit0): If set it to 1, Compression mode will be selected. If set it to 0, Decompression mode will be selected. * Scale Factor Register Control the scale factor of Q-table. Function Quantization table scale factor H L Data S/W reset Previous Value H/W reset 04h E-SCale factor(7:0) ESC(bit7-0): In compression, please setup Q-table scale factor. Q-table each value is divided by this scale factor while quantization is executing. bit7-2 are integer part and bit1-0 are decimal fraction. P/N:PM0363 REV. 1.0, AUG. 25, 1998 18 INDEX MX8810 * Horizontal Dot Cycle Register Horizontal Valid Dot Delay Register Horizontal Valid Dot Width Register Vertical Line Cycle Register Vertical Valid Line Delay Register Vertical Valid Line Width Register Control the valid area which based on image's size and HSYNC /VSYNC. Function H_CYcle(11:0) H_DeLay(10:0) H_WiDth(10:0) V_CYcle(11:0) V_DeLay(10:0) V_WiDth(10:0) Horizontal Dot Cycle Horizontal Effective Delay Horizontal Effective width Horizontal live cycle Horizontal Effective Delay Horizontal Effective Width H Data Data Data Data Data Data L S/W reset Previous Value Previous Value Previous Value Previous Value Previous Value Previous Value H/W reset - HCY, HDL, HWD's unit are dot (pixel). Please setup the values from HSYNC. VCY, VDL, VWD's unit are line. From VSYNC, Please set up the values at the intervals of HSYNC. About each value, please refer to the following figure. HSYNC VSYNC VDL Active Window VWD VCY HDL HWD HCY P.S.) Please precisely set (CLK frequency)/(Horizontal sync frequency)/2-1 to HCY. P/N:PM0363 REV. 1.0, AUG. 25, 1998 19 INDEX MX8810 Set -1 of the value to each register. In case of interlace, please set field size related value. The following table shows the other limitation. Y0Y1 format selected MIN .(HWD+1)2+99 .HDL+HWD+5 bigger value of two 001h 01Fh VDL+VWD+2 010h 007h MAX 7FFh OTHERS HCY HDL HWD VCY VDL VWD 3FFh 3FFh FFFh 7FFh 7FFh 64X-1 8X-1 Other pixel formats selected MIN .(HWD+1)2+49 .HDL+HWD+2 bigger value of two 001h 01Fh VDL+VWD+2 010h 007h MAX 7FFh OTHERS HCY HDL HWD VCY VDL VWD 3FFh 3FFh FFFh 7FFh 7FFh 32X-1 8X-1 P/N:PM0363 REV. 1.0, AUG. 25, 1998 20 INDEX MX8810 * Status Register Presents Internal Operating Status Function End FIFO full FIFO empty Error H End Full Empty Error L Processing not full not empty not error S/W reset H L H L H/W reset H L H L FINish FULll EMPty ERRor FIN(bit7): If 1, means compression data I/F's process is over. If 0, means compression data I/F is in processing. FUL(bit6):If 1, means compression data FIFO is full. If 0, means compression data FIFO is not full. EMP(bit5):If 1, means compression data FIFO is empty. If 0, means compression data FIFO is not empty. ERR(bit4):If 1, means process error. If 0, means it is not process error. Error when compression data FIFO is full in compression and compression data FIFO is empty in decompression. For releasing from error condition, please do compulsorily interrupt the process of hardware reset or software reset. * Interrupt Mask Register Control the interrupt conditions. Function Finish mask Full mask Empty mask Error mask H Output Output Output Output L Mask Mask Mask Mask S/W reset Previous Value Previous Value Previous Value Previous Value H/W reset L L L L MaskFInish MaskFUll MaskEMpty MaskERro MFI(bit7):If 1, interrupt when compression data I/F's process is over. If 0, do not interrupt when compression data I/F's process is over. MFU(bit6):If 1, interrupt when compression data FIFO is full. If 0, do not interrupt when compression data FIFO is full. MEM(bit5): If 1, interrupt when compression data FIFO is empty. If 0, do not interrupt when compression data FIFO is empty. MER(bit4):If 1, interrupt when process error. If 0, do not interrupt when process error. P/N:PM0363 REV. 1.0, AUG. 25, 1998 21 INDEX MX8810 * Y detect Register Cr detect Register Cb detect Register Y detect Mask Register Cr detect Mask Register Cb detect Mask Register Control the chroma-key detection conditions. Function H Y-Detect(7:5) Y detect value Data CR-Detect(7:5) Cr detect value Data CB-Detect(7:5) Cb detect value Data MaskY-Detect(7:5) Y detect mask Detect MaskCR-detect(7:5) Cr detect mask Detect MaskCB-Detect(7:5) Cb detect mask Detect L Data Data Data Mask Mask Mask S/W reset Previous Value Previous Value Previous Value Previous Value Previous Value Previous Value H/W reset 00h 00h 00h 00h 00h 00h YDT(bit7-5): Setup chroma-key detection Y component. CRD(bit7-5): Setup chroma-key detection Cr component. CBD(bit7-5): Setup chroma-key detection Cb component. MYD(bit7-5): Setup "H" at chroma-key detection Y component's bit position. MCR(bit7-5): Setup "H" at chroma-key detection Cr component's bit position. MCB(bit7-5): Setup "H" at chroma-key detection Cb component's bit position. * Y Quantization table C Quantization table Function Y quantization coefficient 00 Y quantization coefficient 63 C quantization coefficient 00 C quantization coefficient 63 H Data Data Data Data L Data Data Data Data S/W reset Previous Value Previous Value Previous Value Previous Value H/W reset Initial Value Initial Value Initial Value Initial Value Y_Q00(7:0) Y_Q63(7:0) C_Q00(7:0) C_Q63(7:0) When standard Q-table is selected, read only. When user define Q-table is selected, read / write both work. The format is 8 bits integer without sign. P/N:PM0363 REV. 1.0, AUG. 25, 1998 22 INDEX MX8810 5-3-5. System Control I/F * Hardware reset When internal circuit is initialized, internal register will be set by default value. When internal circuit is initialized, process compulsory interrupt, releasing process error and clearing internal compression data FIFO will be executed. In the period of hardware reset, all I/O pins will be changed to input mode. * Power down After hardware reset, please power down. Moreover, after releasing from power down, please execute the hardware reset. * Field decision Interlace/Noninterlace is decided by position of 7th line's HSYNC counted from VSYNC. (There is no relationship with equivalent pulse and cut-in pulse of 1st~6th line) In case of interlace, compression/decompression starts from 1st field. * I/O direction Export signal DIR for bus control of pixel I/F and compression data I/F. If "H", Pixel I/F is input and compression data I/F is output. If "L", Pixel I/F is output and compression data I/F is input. P/N:PM0363 REV. 1.0, AUG. 25, 1998 23 INDEX MX8810 5-4. Operations 5-4-1. General Operation Please follow the following steps. 1.Turn on the power. 2. Hardware reset. (Set RESETB "L") 3.Set up the internal registers except command register (address = 00) if the change is necessary. P.S.)In case of changing to DMA compression mode or changing to DMA decompression mode, please set up when the compression data FIFO is empty. In case of EMP in status register (address = 10), the status of compression data FIFO could be investigated. Compression data FIFO could be cleared by hardware reset or software reset. 4.Set "start process (81h)" to command register (address = 00). 5.Refer command register by VSYNC and start the process from 1st field. 6.Set "stop process (01h)" to command register (address = 00). 7.Refer command register by VSYNC and stop after the field processed. 8.If it is necessary, back to step 3. 5-4-2. Process compulsory interrupt, Releasing process error and the clearing operation of compression data FIFO Please follow the following steps. In case of hardware reset: 1. Execute the hardware reset. (set RESETB "L") P.S.1) the value of CPU I/F's internal register will be changed to default value. P.S.2) In the period of input/output of a image compression data, the image's compression data will be invalid if this operation is executed. 2. Back to general operation (5-4-1) step 3. In case of software reset: 1. Set"stop process & software reset (00h)" to command register (address = 00). P.S.1) In the period of input/output of a image compression data, the image's compression data will be invalid if this operation is executed. 2. Set "release software reset (01h)" to command register (address = 00). 3. Back to general operation (5-4-1) step 3. 5-4-3. Power Down Operation The following shows power down operation. 1. Execute hardware reset. (set RESETB "L") P.S.1) CPU I/F's internal register will be set by default value. P.S.2) Execute process compulsory interrupt, realeasing process error and clearing compression data FIFO. 2. Start power down. (set PWDN "H")") 3. Release power down ( set PWDN "L")"L" ) 4. Execute hardware reset. ( set RESETB "L")"L" ) 5. Back to the general operation (5-4-1) step 3. P.S.) The value of CPU I/F's internal register is default value. P/N:PM0363 REV. 1.0, AUG. 25, 1998 24 INDEX MX8810 6. External Circuit 6-1. External Memory for Raster Block Conversion Raster block convert I/F is the interface which connects with external memory for raster order <--> 8x8 block order conversion. he following table shows example of necessary external memory. Selected YOYI Format Horizontal valid dot width 64~256 320~1024 Selected other Format Horizontal valid dot width 32~128 160~512 544~1024 Memory capacity 16 k bits 64 k bits Data width 8 bits 8 bits Pcs 2 2 Memory capacity 16 k bits 64 k bits 256 k bits Data width 8 bits 8 bits 8 bits Pcs 2 2 2 * When block distortion detecting function is used, data width should extend to 9 bits from 8 bits. (expend the memory capacity) The following diagram shows no block distortion detecting function. A14 M0A13~0 M0WE M0OE M0D7~0 M2D A14 M1A13~0 M1WE M1OE M1D7~0 M3D A13~0 WE OE I/O~7 SRAM_1 A13~0 WE OE I/O~7 SRAM_0 P.S.1) To meet the SRAM's write recovery and data hold, please notice each signal's delay skew caused by connection capacity. P.S.2) Set pull up or pull down in unused M2D and M3D passing through a resister.( Please do not directly connect with VCC or GND.) P.S.3) In case that unused signals happened in M0A13~0 and M1A13~0, open it. P/N:PM0363 REV. 1.0, AUG. 25, 1998 25 INDEX MX8810 6-2 Clock Generation Circuit The circuit method for clock generation from NTSC signal is as following: 1.In case of standand NTSC signal (TV broad cast signal, LD playback signal) please use clock generation of linelock method or burstlock method. 2.In case of non-standard NTSC signal, please use clock generation circuit of line lock method. P/N:PM0363 REV. 1.0, AUG. 25, 1998 26 INDEX MX8810 7.Electricity Characteritics 7-1.Absolute Maximum Rating Recommended operating condition Absolute Maximum Rating Item Supply Voltage Input Voltage Output Voltage Operating Temperature Storage Temperature (GND=0V) Symbol VCC Vi Vo Topr Tstg Ratings -0.3~7.0 -0.3~VCC+0.3 -0.3~VCC+0.3 0~70 -55~-150 Units V V V C C Recommended Operating Condition Item Supply Voltage Input Low Voltage Input High Voltage Temperature around Symbol VCC Vil Vih Ta MIN 4.75 0 2.0 0 Ratings TYP 5.0 MAX 5.25 0.8 VCC 70 Units V V V C 25 7-2 D.C. Characteristics DC Characteristics Item Static Consumption Current Operating Consumption Current Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Input High Voltage Input Loww Voltage Capacitance Symbol Ist Iop Iil Ioz Voh Vol Vih Vih (VCC=5V5%,GND=0V,Ta=0~70 C) Ratings Conditions MIN TYP MAX Units Io=0mA 1 mA CLK=28.6MHz,Io=0mA 360 mA Vi=VCC~0v -1 1 uA High-impedance Ioh=1mA or -2mA Iol=2mA or 4mA TTL level input TTL level Output -10 2.4 2.0 0.8 10 0.4 uA V V V V (Ta=25 C,f=1MHz) Ratings TYP MAX 10 10 10 Item Input Capacitance Output Capacitance I/O Capacitance Symbol Cin Cout Cio Conditions Vin=0V Vout=0V Vi0=0V MIN Units pF pF pF P/N:PM0363 REV. 1.0, AUG. 25, 1998 27 INDEX MX8810 7-3 A.C. Characteristics System Control I/F Timing CLK Tch Tcyc Tc1 RESETB Tresw PWDN Tpwdw VSYNC Tvsyw HSYNC Thsyw CLK DIR Tdird Tdird CLK Cycle CLK "H" time CLK "L" time Symbol Tcyc Tch Tcl MIN 35 16 16 TYP MAX Units ns ns ns Conditions RESETB pulse width PWDN pulse width VSYNC pulse width HSYNC pulse width Symbol Tresw Tpwdw Tvsyw Thsyw MIN 2xTcyc 2xTcyc 2xTcyc 2xTcyc TYP MAX *1 *2 Units ns ns ns ns Conditions DIR Output Delay Symbol Tdird MIN 3 TYP MAX 25 Units ns Conditions 50pF *1:12 x Tcyc x (HCY+1) *2:0.5 x Tcyc x (HCY+1) HCY is the value of interual register P/N:PM0363 REV. 1.0, AUG. 25, 1998 28 INDEX MX8810 Pixel I/F Timing Compression CLK PREQ P0D7-0 P1D7-0 P2D7-0 Tprd Tprd Tpds Tpdh * PREQ Output Delay PXD Setup PXD hold Symbol Tprd Tpds Tpdh MIN 3 10 0 TYP MAX 22 Units ns ns ns Conditions 30pF * Please do not change the Input data in this period. Decompression CLK PVALID P0D7-0 P1D7-0 P2D7-0 Tpv1d Tpv1d Tpdd Tprd BLOCK Tblkd Tblkd CRKEY Tcrkd Tcrkd PVALID Output Delay PXD Output Delay BLOCK Output Delay CRKEY Output Delay Symbol Tpv1d Tpdd Tblkd Tcrkd MIN 3 3 3 3 TYP MAX 22 22 22 22 Units ns ns ns ns Conditions 30pF 30pF 30pF 30pF P/N:PM0363 REV. 1.0, AUG. 25, 1998 29 INDEX MX8810 Raster Block Convert I/F Timing CLK M0A14-0 M1A14-0 Tmad Tmad M0WEB M1WEB M0D7-0 M1D7-0 M2D,M3D Output M0OEB M1OEB M0D7-0 M1D7-0 M2D,M3D Input Tmoed Tmoed Tmwid Tmwhd Tmdd Tmdd Tmds Tmdh MAX Output Delay MXWEB Falling Delay MXWEB Rising Delay MXD Output Delay MXOEB Output Delay MXD Setup MXD Hold Symbol Tmad Tmw1d Tmwhd Tmdd Tmoed Tmds Tmdh MIN 3 3 3 3 3 2 3 TYP MAX 18 15 15 37 25 Units ns ns ns ns ns ns ns Conditions 30pF 30pF 30pF 30pF 30pF P/N:PM0363 REV. 1.0, AUG. 25, 1998 30 INDEX MX8810 Compression Data I/F Timing Compression in Synchronous Mode CLK CVALID Tcvld Tcvld CDATA31-0 Tcd1d Tcd1d EOF Teo1d Teo1d DTENDB Tdt1d Tdt1d Symbol CVALID Output Delay CDATA Output Delay EOF Output Delay DTENDB Output Delay MIN Tcrld Tcd1d Teo1d Tdt1d TYP 3 3 3 3 MAX Units 22 22 22 22 Conditions ns ns ns ns 50pF 50pF 50pF 50pF Decompression in Synchronous Mode CLK CREQ Tcrqd Tcrqd CDATA31-0 Tcd1s Tcd1h Symbol CREQ Output Delay CDATA Setup CDATA Hold P.S:CREQ is a level signal. Do not use edge trigger. MIN Tcrqd Tcd1s Tcd1h TYP 3 10 0 MAX Units 50 Conditions ns 30pF ns ns P/N:PM0363 REV. 1.0, AUG. 25, 1998 31 INDEX MX8810 Compression in DMA Mode DMAREQB Tdrqd DMARDB Tdrdh WAITB Tdrd1w Tdrdhw Twaid CDATA31-0 Tcd2d DTENDB Tdt2d EOF Teo2d Teo2d Teo2d Teo2d Tdt2d Tdt2d Tdt2d Tcd2d Tcd2d Tcd2d Z Z DMAREQB Output Delay DMARDB "L" time DMARDB "H" time DMARDB CDTAT Output Delay DTENDB Output Delay EOF Output Delay WAITB Output Delay Symbol Tdrqd Tdrdlw Tdrdhw Tdrdh Tcd2d Tdt2d Teo2d Twaid MIN 3 2XTcyc+3 2XTcyc+3 2XTcyc+3 3 3 3 3 TYP MAX 2XTcyc+22 22 2XTcyc+22 22 22 Units ns ns ns ns ns ns ns ns Conditions 50pF 50pF 50pF 50pF P/N:PM0363 REV. 1.0, AUG. 25, 1998 32 INDEX MX8810 Decompression in DMA Mode DMAREQB Tdrqd DMAWRB Tdwrh WAITB Tdwr1w Tdwrhw Twaid CDATA31-0 Tcd2s Tcd2h Tcd2s Tcd2h Z DMAREQB Output Delay DMAWRB "L" time DMAWRB "H" time DMARDB CDTAT CDATA WAITB Output Delay Symbol Tdrqd Tdwrlw Tdwrhw Tdwrh Tcd2s Tcd2h Twaid MIN TYP 3 2XTcyc+3 2XTcyc+3 2XTcyc+3 10 0 3 MAX 2XTcyc+22 22 Units ns ns ns ns ns ns ns Conditions 50pF 50pF P/N:PM0363 REV. 1.0, AUG. 25, 1998 33 INDEX MX8810 CPU I/F Timing WRITE ADD7-0 Tads CSB WRB Tcss Tcsh Twrw DATA7-0 Tdats Tdath Tadh ADD setup ADD hold CSB setup CSB hold WRB pulse width DATA setup DATA hold Symbol Tads Tadh Tcss Tcsh Twrw Tdats Tdath MIN 0 0 10 0 20 20 0 TYP MAX Units ns ns ns ns ns ns ns Conditions P/N:PM0363 REV. 1.0, AUG. 25, 1998 34 INDEX MX8810 READ ADD7-0 Tads CSB RDB Tcss Tcsh Tadh DATA7-0 Tdatd Tdatd ADD setup ADD hold CSB setup CBS hold DATA Output Symbol Tads Tadh Tcss Tcsh Tdatd MIN 0 0 35 10 0 3 TYP MAX 22 Units ns ns ns ns ns ns Conditions *1 *2 50pF *1:When Reading Quantization Table *2:When Reading Registers which is not Quantization Table P/N:PM0363 REV. 1.0, AUG. 25, 1998 35 INDEX MX8810 Interrupt Request CLK INTB INTB output delay Symbol Tintd MIN TYP MAX 22 Units ns Conditions 50pF AC test condition Input voltage timing 2.4V 1.5V 0.4V Tr=5ns, Tf=5ns 1.5V 0.8V Output judgenent voltage 2.0V P/N:PM0363 REV. 1.0, AUG. 25, 1998 36 INDEX MX8810 8.Package Appearance The following figure is Package's Appearance A B ITEM A B C D E F G H I J K L M N O P NOTE: MILLIMETERS 31.20 .30 28.00 .10 28.00 .10 31.20 .30 25.35 1.33 [REF.] 1.33 [REF.] .30 [Typ.] .65 [Typ.] 1.60 [REF.] .80 2.0 .15 [Typ.] .10 max. 3.35 max. .10 min. 3.68 max. INCHES 1.228 .012 1.102 .004 1.102 .004 1.228 .012 .999 .052 [REF.] .052 [REF.] E C D 120 121 81 80 .012 [Typ.] .026 [Typ.] .063 [REF.] .031 .008 .006 [Typ.] .004 max. .132 max. .004 min. .145 max. G H I J N L M K O P F 160 1 41 40 Each lead centerline is located within .25 mm[.01 inch] of its true position [TP] at maximum material condition. P/N:PM0363 REV. 1.0, AUG. 25, 1998 37 INDEX MX8810 MACRONIX INTERNATIONAL CO., LTD. HEADQUARTERS: TEL:+886-3-578-8888 FAX:+886-3-578-8887 EUROPE OFFICE: TEL:+32-2-456-8020 FAX:+32-2-456-8021 JAPAN OFFICE: TEL:+81-44-246-9100 FAX:+81-44-246-9105 SINGAPORE OFFICE: TEL:+65-747-2309 FAX:+65-748-4090 TAIPEI OFFICE: TEL:+886-3-509-3300 FAX:+886-3-509-2200 MACRONIX AMERICA, INC. TEL:+1-408-453-8088 FAX:+1-408-453-8488 CHICAGO OFFICE: TEL:+1-847-963-1900 FAX:+1-847-963-1909 http : //www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice. 38 |
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